1. Field of the Invention
The present invention relates to an improvement in undershoot in a voltage regulator.
2. Description of the Related Art
FIG. 3 illustrates a circuit diagram of a related-art voltage regulator. The related-art voltage regulator includes an error amplifier 110, PMOS transistors 120, 201, and 204, NMOS transistors 202, 203, and 205, resistors 231, 232, 233, and 234, a comparator 210, an inverter 211, an offset voltage generation circuit 212, a power supply terminal 100, a ground terminal 101, a reference voltage terminal 102, and an output terminal 103.
The error amplifier 110 controls a gate of the PMOS transistor 120, and an output voltage Vout is thereby output from the output terminal 103. The output voltage Vout has a value determined by dividing a voltage of the reference voltage terminal 102 by a total resistance value of the resistor 231 and the resistor 232 and multiplying the resultant value by a resistance value of the resistor 232. When an undershoot occurs, the comparator 210 compares a voltage determined by adding a voltage Vo of the offset voltage generation circuit 212 to a divided voltage Vfb with a reference voltage Vref. When the voltage determined by adding the offset voltage Vo to the divided voltage Vfb becomes lower than the reference voltage Vref, the comparator 210 outputs “High”, thereby turning on the NMOS transistor 203. When an output current IOUT is smaller than an overcurrent IL, the NMOS transistor 202 is turned on to pull down a gate of the PMOS transistor 120, thereby controlling the output voltage Vout to be increased. Consequently, the undershoot is improved, and undershoot characteristics of the voltage regulator are improved (see, for example, Japanese Patent Application Laid-open No. 2010-152451).
In the related-art voltage regulator, however, there is a problem in that it may take time to control so that a predetermined output voltage Vout may be output from the state in which an undershoot occurs and the PMOS transistor 120 is turned fully on. Further, there is another problem in that an output current may become excessive to increase the output voltage Vout while the output voltage Vout is controlled to be a predetermined output voltage from the state in which an undershoot occurs and the PMOS transistor is turned fully on.